1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device using multiple exposure.
2. Description of the Related Art
A nonvolatile semiconductor memory is exemplified as one of semiconductor memory devices. In recent years, there has been a growing demand for the nonvolatile semiconductor memory used as a data storage device. A NOR-type flash memory or a NAND-type flash memory is known as a typical nonvolatile semiconductor memory.
In order to increase memory capacities of these flash memories, downsizing of an element device is carried out. In particular, the NAND-type flash memory is advantageous in downsizing, and thus, increasing its capacitance is underway.
The NAND-type flash memory comprises a memory cell section and a periphery circuit section provided at the periphery of the memory cell section. The memory cell section comprises a comparatively simple and periodic line and space pattern (L&S pattern). The L&S pattern is suitable for downsizing. Therefore, the performance of an exposure apparatus is improved, thereby making it possible to form a memory cell section that includes dense and large capacitance memory cells. On the other hand, the peripheral circuit section is not suitable for downsizing because it generally comprises an irregular pattern.
In a process for forming a pattern of a general memory device, the memory cell section and the peripheral circuit section are exposed at the same time to form a circuit pattern (Jpn. Pat. Appln. KOKAI Publication No. 10-154802). Therefore, the downsizing of the pattern in the memory cell section is limited by the pattern forming capability of the peripheral circuit section.